Modern semiconductor design relies heavily on the use of various software tools, which perform the tasks required to implement a desired circuit design onto silicon. In general, the design process begins with a definitional design which, as its name implies, describes the desired logical, timing and power parameters of the desired circuit. The definitional design is typically implemented in a computer readable file written in hardware description language ("HDL") such as Verilog, HDL, VHDL, DSL, etc. The definitional design is also referred to as a behavioral description or model of the circuit. The HDL file is then provided to two categories of tools, which are used to test the design and convert the HDL into other computer readable files needed to actually fabricate the circuit.
The first category includes simulation tools which are used to test the circuit's logical performance, i.e., whether the circuit generates the desired output signals in response to a predefined set of input signals. The simulation tools are typically software implemented processes which are run on a workstation or other computer processors. These tools use the HDL file to create a software model of the definitional design. A variety of simulated inputs may then be applied to the software model. The resulting outputs of the model are recorded and compared to expected outputs to determine whether the definitional design produced the logical results required. Since simulation is concerned, primarily, with the logical performance of the design, simulation tools are largely technology independent, i.e., the design has not been mapped to specific cell libraries which contain data for constructing actual electronic components according to known fabrication processes. Commercially available simulation tools include "SpeedSim," commercially available from Quickturn, Corp.
The second category includes synthesis and implementation tools. Like simulation tools, synthesis and implementation tools are typically implemented in software which runs on a workstation or other computer processor. However, these tools are highly technology dependent and are used to create an implementation of the circuit components onto the chip. Specifically, synthesis tools are used to generate the mapped logic "netlist," which contains a description of the gates and interconnections between gates for the desired circuit. Suitable tools are familiar to those of skill in the art, such as "SYNOPSYS DESIGN COMPILER" commercially available from Synopsys Corp.
The netlist from the synthesis tool is then provided to a placement tool, such as "QPLACE," commercially available from Cadence, Corp. The placement tool determines where the gates of the circuit will be physically located within a location on the chip which has been predesignated to contain the circuit. This location is referred to as the "image."
After the circuit has been placed, the data from the placement tool is provided to a router, such as "CELL3," commercially available from Cadence, Corp. The router generates the fabrication data required to construct the metal lines on the chip that connect the components of the circuit together. After routing, all the files containing the computer data required to fabricate an implementation of the circuit are available. This is referred to as the final design data. The final design data is then sent to manufacturing where the final design data from other circuits on the chip are integrated together, and the actual chip is manufactured.
Of course, significant testing must be performed during the course of synthesizing and implementing the desired circuit to ensure the final design data is accurate. Otherwise, the fabricated chip will not perform as the designers intended. This is described in greater detail with respect to FIG. 1A.
FIG. 1A is a flow chart 100 illustrating a conventional synthesis and implementation process. The process begins in step 102 with the development of the logical behavior, timing constraints, power consumption, physical device size and other requirements for a desired semiconductor circuit. These requirements are purely a matter of design choice and are selected in accordance with the features and performance characteristics desired in the finished integrated circuit. A circuit design engineer then uses the requirements as guidelines to create the HDL description file. The HDL file, as discussed previously, is a computer readable file that contains data representing the necessary logical, timing and other parameters of a circuit which satisfies the requirements. The HDL file is sometimes referred to as the "behavioral model" since it specifies the logical behavior of the circuit. The HDL file is then provided as input to the synthesis tool in step 106.
The synthesis tool, sometimes referred to as the "synthesizer", in step 106 generates a hardware design netlist for the circuit by mapping the HDL description to "standard logic cells", i.e., predefined blocks of electronic components which are connected together to form a suitable implementation of the circuit defined by the HDL description file. The mapping process is well understood in the art. Specifically, the netlist specifies the nature of each electronic component in a generic fashion. For example, one component may be a simple AND gate. The synthesis tool then selects a specific AND gate in the netlist. This process is repeated for every electronic component in the generic net list until all the electronic components are associated with, or mapped, to actual circuits from the cell library. At this point, the net list is sometimes referred to as a mapped netlist. A variety of suitable standard logic cells are commercially available to those of skill in the art. More specifically, a cell selected from a cell library is a basic building block for a circuit design. Within a cell library, the individual cells are typically defined at various levels of abstraction in a hierarchical order. At the lowest level, a cell may be a particular NMOS or PMOS transistor. At a somewhat higher level, a cell may be a collection transistors connected together to create various logical gates.
The lowest level of cells used in a particular design methodology are referred to as "leaf cells." Integrated circuits are built by assembling collections of leaf level cells as building blocks. These building blocks are typically well known circuit components such as multiplexors ("MUXes"), registers, arrays, comparators, and simple Boolean circuits such as ANDs, ORs, AOs, and AOIs. In the general case, these leaf level building blocks can be integrated with any number of levels of hierarchy. For example, a few registers, MUXes and Boolean gates could be used to create a circuit component which performs a particular sub-function of the circuit. This collection could be manipulated by other circuit design tools as a package for purposes of placement onto an area of the chip and integration with other cells or electronic components of the integrated circuit. Next, this package could be used as if it were itself a basic building block to construct additional circuit components which provide an even higher level function on the chip. By continuing in this fashion, it is possible to eventually create a circuit which provides the level of function required by the chip as a whole.
With respect to the exemplary "PowerPC" family of processors, commercially available from IBM and Motorola Corporations, the circuits are generally designed using 2 to 4 levels of hierarchy. Collections of Boolean functions are typically created, and placed in their own level of hierarchy. Each of the collections is called an "RLM" or Random Logic Macro. RLMs are used to implement control logic function. Collections of data flow elements such as MUXes, registers, arrays, etc. are placed into levels of hierarchy that are referred to as "super macros." Super macros and RLMs differ only by convention, that is, Boolean control logic cells are placed in RLMs, and data flow elements are placed in super macros.
After the synthesizer has mapped the HDL description file to a specific technology, it produces a mapped netlist as shown in step 108. As discussed, the netlist produced by the synthesis tool lists all cells in the circuit and the interconnections between them. The interconnections between the components are referred to as "nets." This is depicted in FIG. 1B which shows a component, in this case and an AND gate 10, which is connected by net 12 to an inverter 14 and to OR gate 18. Also, by way of definition, the term "fan-in" is used to refer to the number of inputs that are provided to an individual circuit component. Thus, it will be noted that AND gate 10 has three inputs, 10a, 10b and 10c. Therefore, the fan-in to AND gate 10 is three. Similarly, the term "fan-out" refers to the number of outputs that are driven by a single component. Referring again to AND gate 10, it is seen that the gate drives two separate outputs, i.e., one for inverter 14 and one for OR gate 18. Accordingly, AND gate 10 is said to have a fan-out of two.
The synthesizer uses the design requirements set forth in the HDL description file as it selects and connects the various individual circuit components from the technology library so that the circuit defined by the netlist 108 meets all the design requirements. Often, the most difficult requirements to meet are the timing requirements for the circuit. The timing requirements specify the permissible propagation delay time for signals to travel through the various signal paths in the circuit. A path is a sequence of components and nets through which a particular signal travels. For example, referring again to FIG. 1B, it is seen that whenever a clock signal CLK is received at clocked register 20, a signal is provided from the output of register 20 to an input of register 22 through a path consisting of net 10b, AND gate 10, net 12, inverter 14 and net 24. The time required for a signal to travel from register 20 to register 22 is referred to as the path or propagation delay.
Of course, all paths in the circuit have a designed acceptable propagation delay time. However, for reasons which will be discussed in greater detail herein, the propagation delay time for a path as designed by the synthesizer is often different than the actual delay time of the path after the placement tool has placed it in the image. The difference between the designed delay time and the actual delay time is referred to as the "slack". If the slack is positive or zero, then the path meets the design criteria. If the slack is negative, then the propagation delay time is unacceptable and changes must be made to the circuit to correct its timing performance.
In order to ensure that the circuit defined by the netlist meets all timing requirements before it is provided to the placement tool in step 110, the synthesizer makes use of a timing analyzer as it selects and assembles the circuit components in step 106. Various suitable timing analyzers are commercially available to those of skill in the art, for example, one common timing analyzer is "MOTIVE", commercially available from Viewlogic, Corp. A detailed discussion of the various techniques employed by different timing analyzers is not necessary for a complete understanding of the present invention, and accordingly, only the following general discussion is provided in order to better illustrate the shortcomings of the present techniques.
Referring again to FIG. 1B, it is seen that the propagation delay experienced by a signal traveling from register 20 to register 22 is the sum of the propagation delay due to net 10b, AND gate 10, net 12, inverter 14 and net 24. Since AND gate 10 and inverter 14 are predesigned circuit components from a standard cell library, their propagation delay times are accurately known for any given load. However, the propagation delay time due to nets 10b, 12 and 24 are more problematic.
More particularly, connections between circuit components are typically formed by metal lines on the integrated circuit. All metal lines on an integrated circuit have an inherent capacitance which adds loading to the driving circuit, thus delaying the propagation time of the signal. Moreover, the longer the metal line, the greater the capacitance it has. Thus, it should be clear that the propagation delay time for a signal path, such as the one discussed with respect to FIG. 1B, cannot be accurately determined unless the wire length of the nets in the path are accurately known.
However, since the components of the circuit have not yet been placed, i.e., associated with specific locations in the image, it is impossible for the synthesizer at this point in the process to know the lengths of the nets in the circuit. Thus, the synthesizer in step 106 must rely on estimates of the wire length to generate the "wire models" used to calculate the capacitance, and hence, the propagation delay of the individual paths of the circuit. Generally, these wire models contain wire lengths which are estimated on a statistical basis according to the number of fan-outs found in the individual nets, although other techniques are also known to those of skill in the art.
After the netlist 108 has been generated using estimated wire models, it is provided as input to the placement tool in step 110. Placement techniques are well known in the art. For example, although there are differences, conventional placement tools typically utilize either a variation of a min-cut algorithm, such as that described in Ulrich, "A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph," proceedings of the 16th Design Automation Conference, 1979, pages 1-10, or a thermal annealing analog algorithm, such as that described in Kirkpatrick, et al., "Optimization by Simulated Annealing" Science, Vol. 220, No. 4598, May 13, 1983, pages 671-680, both of which are incorporated herein by reference.
It is generally a goal of the placement tool to arrange the components of the circuit in the image in order to minimize the area consumed by the circuit and provide improvements in the function of the circuit, such as cycle time. After the placement tool has determined a location for each component of the circuit in the image, this data is provided to the router in step 112. Naturally, as the components in the circuit are placed on different locations in the image, the length of the nets connecting individual circuit components change accordingly.
The router uses the component placement data received from the placement tool and the netlist to generate a file representing the required metal connections for the cells in the circuit. After routing in step 112, all data required to generate the final data for fabrication of the circuit is available.
However, the final design must be re-checked in step 116 to ensure that it meets timing requirements before the circuit is fabricated in step 120. This is because the timing analyzer used during synthesis in step 106 relied on estimates of the actual wire lengths, rather than the actual wire lengths determined during placement.
If in step 116 it is determined that the circuit as placed in step 110 no longer meets timing requirements, then the process must proceed to step 118 where some aspect of the design is corrected. As a matter of design choice, a circuit designer may make changes in any one of steps 104, 106, 108, 110, or 112, or some combination thereof, in order to correct the timing of the circuit. For example, changes can be made in the actual circuit design itself and reflected in the HDL description file. Then, steps 104-114 are repeated. Alternately, various run parameters can be changed to influence the operation of the synthesis tool in step 106. This will produce a somewhat different netlist and steps 106-114 can be repeated. Numerous other modifications are possible in steps 104-112 and will be familiar to those of skill in the art.
However, regardless of the changes made it should be clear that the resulting final design in step 114 must, again, be checked to ensure that it meets timing constraints in step 116. If not, then another iteration through the process is required. This process is repeated until the circuit as synthesized in step 106 and placed in step 110 meets the timing requirements in step 116. The resulting final design data may then be sent to a semiconductor manufacturer for fabrication of the integrated circuit. When the final design meets the timing constraint in step 116, it is said that timing convergence is achieved.
Timing convergence between synthesis and placement remains a challenge for advanced microprocessor designs for several reasons. First, while the wire models used during synthesis provide a reasonable prediction of the average wire length in the design, they are usually quite poor at predicting the actual wire lengths of a particular set of nets. Therefore, for the few nets on a critical path the prediction can be quite inaccurate, and the associated path lengths may be significantly longer than predicted, resulting in a negative slack and require several re-iterations of synthesis and placement.
More particularly, synthesis produces a netlist based on timing considerations but without actual physical design considerations. As a result, the synthesizer might expect a particular net to be "short" with low capacitance while, in fact, after placement this net might be relatively "long". Thus, the other decisions made by the synthesizer regarding the net, such as the selection of a particular cell, may be undesirable.
Second, the wire delay and gate delay can be of almost equal significance in submicron electronic circuit designs. Even when designers can feed wire capacitances from a placed and wired design for re-synthesis, it is not assured that wire capacitances remain the same after a set of logic transformations. This prolongs the timing convergence process by forcing circuit designers to do multiple iterations between the synthesis and placement steps in the circuit design process.
These errors are caught during the chip level timing analysis in step 116 where the actual interconnect length is used. However, this presents the dilemma that, in order to fix the problem, a change in the circuit described by the netlist is required, but such a change results in disturbing the placed and wired design generated by the placement tool. Thus, a new netlist is generated every time a change to the circuit is made. This provides still further timing conversion problems because the circuit that just underwent a logic transformation, such as re-powering, may drive a short net in the new placement, while another circuit that used to drive a short net in the previous iteration may now be forced to drive a long net. Thus, while the iteration solves the problem with respect to the first circuit, it has now created a new problem with respect to the second circuit. Thus, more iterations are required.